(1) Field of the Invention
The invention relates to a method of manufacturing an integrated circuit device, and, more particularly, to a novel method of singulating integrated circuit die from a semiconductor wafer.
(2) Description of the Prior Art
Integrated circuits are typically fabricated on large, thin wafers of semiconductor material, such as silicon. Tens, hundreds, or even thousands of independent and identical integrated circuits may be formed on a single wafer. It is this mass production of identical devices on a single wafer that gives integrated circuit manufacturing its economic advantage. This economic advantage of mass production of product on each wafer covers the large costs associated with the manufacturing facility, or fab, and the high technology equipment required to process and to test the products.
Referring now to FIG. 1, a prior art integrated circuit wafer 10 is shown. Integrated circuit wafers typically range in size from about 4 inches to about 16 inches or larger. In a typical configuration, a large number of circuit locations 14, also called die locations 14, are arranged across the wafer 10 in columns and rows. In the exemplary wafer, the die 14 are of a single size though each location may actually comprise different designs or products. Sometimes larger or smaller circuits 14 will be formed by combining several die locations or by dividing a single die location. However, as will be shown in the following, these multiple sized die cannot be independently singulated and removed from the integrated circuit wafer 10 without sacrificing other die locations.
In the typical manufacturing sequence, the integrated circuit wafer 10 is processed to completion of all levels. Next, the wafer 10 is tested using an automated tester. During this wafer-level test, each die location is probed and is tested for functionality and for parametric performance. The automated tester will then store the test results and may use a marking system to label the die locations 14 on the wafer 10 as either PASS or FAIL. For example, the automated tester can place an ink dot on every die location that has FAILED the test while leaving die locations that have PASSED the test as unmarked. At this point, the wafer 10 is prepared for the process of singulation.
Referring now to FIG. 2, a prior art example of singulation is shown. The integrated circuit wafer 10, shown here in cross section, is attached to a frame 18 comprising an adhesive tape. This tape frame 18 holds the wafer 10 in place during the singulation process. Next, a diamond bladed saw 26 is used to cut through the wafer in a first direction. Note that the substrate of the wafer 10 is typically a continuous crystalline piece of silicon. Each die location 14, as shown by DIE1-DIE5, is actually a part of this same semiconductor substrate 10. Surface films 22, such as dielectric layers and conductive layers, are formed overlying the surface of the substrate 10 and are may or may not be contiguous across different die. The spaces between the surface films 22 are typically called “streets” and are the target locations for the diamond bladed saw 26. The saw 26 cuts completely through the substrate 10 to separate, for example, all of the die in the row containing DIE1 from all of the die in the row containing DIE2, and so on.
Referring now to FIG. 3, the singulation process of the prior art is shown in further detail in a top view. The wafer 10 is mounted on the adhesive tape frame 18. The diamond bladed saw, not shown, cuts across the wafer in a series of horizontal passes 30 and vertical passes 34. With each horizontal pass 30 from one side of the wafer 10 to the other side of the wafer 10, two rows of die locations are separated. With each vertical pass 34 from one side of the wafer 10 to the other side of the wafer 10, two columns of die locations are separated. Finally, after the completion of all of the horizontal passes 30 and vertical passes 34, all of the circuit die 14 are separated, or singulated, from the wafer 10.
Next, further processes may be used to select and to remove the good die (those labeled as PASSED) from the wafer while leaving behind the bad die (those labeled as FAILED). In one process, good die are removed from the adhesive tape frame and placed onto packages. Referring now to FIG. 4, a prior art packaged integrated circuit is illustrated. The package 42 comprises a chip carrier means, such as a metal or ceramic surface, onto which the circuit die 38 is fixably mounted. The package 42 further comprises signal pins 46 which can physically interface critical signals into and out from (I/O) the integrated circuit 38. These package pins 46 are physically connected to the signals on the integrated circuit die 38 using, for example, very fine gold wire 54. This gold wire 54 is ultrasonically welded from pads on the integrated circuit die 38 to pads 50 on the package 42.
The above described package device can suffer from mechanical overstress. It is difficult to perfectly match the thermal conductivity of the integrated circuit die 38 and of the various components of the package 42. Therefore, thermal cycling can induce significant thermal stress into the die 38 or into the die 38 and package interface 42. This thermal stress is highest at boundaries and at corners. Therefore, the corners 58 of the die 38 are the highest mechanical stress points and are prone to mechanical failure (cracking or shearing). In addition, the concentration of wire bonds and related bond stress is highest in the corners of the die 38 and results in mechanical failure at these locations.
As described above, the present die singulation method creates rectangular die with sharp, 90° corners. However, it would appear to be advantageous to go away from rectangular-shaped, sharply cornered die in packaged integrated circuit applications.
Several prior art inventions relate to methods or apparatus for cutting semiconductor substrates. U.S. Pat. No. 6,586,707 B2 to Boyle et al describes a method and an apparatus for micromachining a semiconductor substrate. Ultraviolet and visible light lasers are used to machine various features into semiconductor substrates. U.S. Pat. No. 6,420,776 B1 to Glenn et al teaches a method and a structure where a laser scribe machine is used to singulate die on a semiconductor substrate. However, this method shows cutting across the wafer in rows and columns (FIGS. 3A and 6).